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HD6432351 Datasheet(PDF) 406 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 406 Page - Renesas Technology Corp |
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406 / 1025 page ![]() Section 9 I/O Ports Rev. 3.00 Sep 15, 2006 page 372 of 988 REJ09B0330-0300 Modes 4 and 5 In modes 4 and 5, the lower 5 bits of port A are designated as address outputs automatically, while the upper 3 bits function as address outputs or input ports and interrupt input pins. Input or output can be specified individually for the upper 3 bits. Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Port A pin functions in modes 4 and 5 are shown in figure 9.9. A23 (output) A22 (output) A21 (output) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) PA7 (input)/IRQ7 (input) PA6 (input)/IRQ6 (input) PA5 (input)/IRQ5 (input) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) When PADDR = 1 When PADDR = 0 Port A Figure 9.9 Port A Pin Functions (Modes 4 and 5) |
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