HD6432351 datasheet(528/1025 Pages) RENESAS

528 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 494 of 988

REJ09B0330-0300

10.7

Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation.

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.48 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width

Notes: Phase difference and overlap

Pulse width

: 1.5 states or more

: 2.5 states or more

Figure 10.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Caution on Period Setting

When counter clearing by compare match is set, TCNT is cleared in the final state in which it

matches the TGR value (the point at which the count value matched by TCNT is updated).

Consequently, the actual counter frequency is given by the following formula:

f =

(N + 1)

Where f: Counter frequency

φ: Operating frequency

N: TGR set value

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