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HD6432351 Datasheet(PDF) 531 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 531 Page - Renesas Technology Corp |
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531 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 497 of 988 REJ09B0330-0300 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10.51 shows the timing in this case. Compare match signal Write signal Address φ TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N+1 Inhibited Figure 10.51 Contention between TGR Write and Compare Match |
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