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HD6432351 Datasheet(PDF) 535 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 535 Page - Renesas Technology Corp |
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535 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 501 of 988 REJ09B0330-0300 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.55 shows the timing in this case. Input capture signal Write signal Address φ TCNT Buffer register write cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 10.55 Contention between Buffer Register Write and Input Capture |
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