HD6432351 datasheet(543/1025 Pages) RENESAS

543 / 1025 page

Section 11 Programmable Pulse Generator (PPG)

Rev. 3.00 Sep 15, 2006 page 509 of 988

REJ09B0330-0300

11.2

11.2.1

Next Data Enable Registers H and L (NDERH, NDERL)

NDER15

R/W

NDER14

R/W

NDER13

R/W

NDER12

R/W

NDER11

R/W

NDER8

R/W

NDER10

R/W

NDER9

R/W

Bit

Initial value

R/W

NDERH

NDER7

R/W

NDER6

R/W

NDER5

R/W

NDER4

R/W

NDER3

R/W

NDER0

R/W

NDER2

R/W

NDER1

R/W

NDERL

Bit

Initial value

R/W

NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a

bit-by-bit basis.

If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically

transferred to the corresponding PODR bit when the TPU compare match event specified by PCR

occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from

NDR to PODR and the output value does not change.

NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They

are not initialized in software standby mode.

NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or

disable pulse output on a bit-by-bit basis.

Bits 7 to 0

NDER15 to NDER8

Description

Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not

transferred to POD15 to POD8)

(Initial value)

Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred

to POD15 to POD8)

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