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HD6432351 Datasheet(PDF) 597 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 597 Page - Renesas Technology Corp |
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597 / 1025 page ![]() Section 13 Serial Communication Interface (SCI) Rev. 3.00 Sep 15, 2006 page 563 of 988 REJ09B0330-0300 13.2.8 Bit Rate Register (BRR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 0 1 R/W 2 1 R/W 1 1 R/W Bit Initial value R/W : : : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 13.3 shows sample BRR settings in asynchronous mode, and table 13.4 shows sample BRR settings in clocked synchronous mode. Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) φφφφ = 2 MHz φφφφ = 2.097152 MHz φφφφ = 2.4576 MHz φφφφ = 3 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 — 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 — 0 2 — 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 — 0 1 — 0 2 0.00 38400 0 1 — 0 1 — 0 1 0.00 — — — |
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