HD6432351 datasheet(679/1025 Pages) RENESAS

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Section 15 A/D Converter

Rev. 3.00 Sep 15, 2006 page 645 of 988

REJ09B0330-0300

15.2

15.2.1

A/D Data Registers A to D (ADDRA to ADDRD)

AD9

Bit

Initial value

R/W

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

—

There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of

A/D conversion.

The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected

channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte

(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and

stored. Bits 5 to 0 are always read as 0.

The correspondence between the analog input channels and ADDR registers is shown in table

15.3.

ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower

byte, data transfer is performed via a temporary register (TEMP). For details, see section 15.3,

Interface to Bus Master.

The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop

mode.

Table 15.3 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

Group 0

Group 1

A/D Data Register

AN0

AN4

ADDRA

AN1

AN5

ADDRB

AN2

AN6

ADDRC

AN3

AN7

ADDRD

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