HD6432351 datasheet(742/1025 Pages) RENESAS

742 / 1025 page

Section 21 Electrical Characteristics

Rev. 3.00 Sep 15, 2006 page 708 of 988

REJ09B0330-0300

21.3.1

Clock Timing

Table 21.4 lists the clock timing

Table 21.4 Clock Timing

Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC,

VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications),

Ta = –40 to +85°C (wide-range specifications)

Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC,

VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications),

Ta = –40 to +85°C (wide-range specifications)

Condition A

Condition B

Item

Symbol Min

Max

Min

Max

Unit

Test Conditions

Clock cycle time

tcyc

100

500

Figure 21.4

Clock high pulse width

tCH

—

Figure 21.4

Clock low pulse width

tCL

—

Clock rise time

tCr

—

Clock fall time

tCf

—

Clock oscillator setting

time at reset (crystal)

tOSC1

—

Figure 21.5

Clock oscillator setting time

in software standby (crystal)

tOSC2

—

Figure 20.2

External clock output

stabilization delay time

tDEXT

500

—

500

—

µs

Figure 21.5

tCH

tCf

tcyc

tCL

tCr

Figure 21.4 System Clock Timing

HD6432351 Datasheet(PDF) 742 Page - Renesas Technology Corp

HD6432351 Datasheet(HTML) 742 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL