HD6432351 datasheet(746/1025 Pages) RENESAS

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Section 21 Electrical Characteristics

Rev. 3.00 Sep 15, 2006 page 712 of 988

REJ09B0330-0300

21.3.3

Bus Timing

Table 21.6 lists the bus timing.

Table 21.6 Bus Timing

Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC,

VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications),

Ta = –40 to +85°C (wide-range specifications)

Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC,

VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications),

Ta = –40 to +85°C (wide-range specifications)

Condition A

Condition B

Item

Symbol

Min

Max

Min

Max

Unit

Test Conditions

Address delay time

tAD

—

Address setup time

tAS

0.5

tcyc –30

—

0.5

tcyc –15

—

Figure 21.8 to

Figure 21.15

Address hold time

tAH

0.5

tcyc –20

—

0.5

tcyc –10

—

Precharge time

tPCH

1.5

tcyc –40

—

1.5

tcyc –20

—

CS delay time 1

tCSD1

—

CS delay time 2

tCSD2

—

AS delay time

tASD

—

RD delay time 1

tRSD1

—

RD delay time 2

tRSD2

—

CAS delay time

tCASD

—

Read data setup time tRDS

—

Read data hold time

tRDH

—

Read data access

time1

tACC1

—

1.0

tcyc –50

—

1.0

tcyc –25

Read data access

time2

tACC2

—

1.5

tcyc –50

—

1.5

tcyc –25

Read data access

time3

tACC3

—

2.0

tcyc –50

—

2.0

tcyc –25

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