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HD6432351 Datasheet(PDF) 756 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 756 Page - Renesas Technology Corp |
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756 / 1025 page ![]() Section 21 Electrical Characteristics Rev. 3.00 Sep 15, 2006 page 722 of 988 REJ09B0330-0300 21.3.4 DMAC Timing Table 21.7 lists the DMAC timing. Table 21.7 DMAC Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions DREQ setup time tDRQS 40 — 30 — ns Figure 21.21 DREQ hold time tDRQH 10 — 10 — TEND delay time tTED — 40 — 20 Figure 21.20 DACK delay time 1 tDACD1 — 40 — 20 ns DACK delay time 2 tDACD2 — 40 — 20 Figure 21.18, Figure 21.19 |
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