HD6432351 datasheet(760/1025 Pages) RENESAS

760 / 1025 page

Section 21 Electrical Characteristics

Rev. 3.00 Sep 15, 2006 page 726 of 988

REJ09B0330-0300

21.3.5

Timing of On-Chip Supporting Modules

Table 21.8 lists the timing of on-chip supporting modules.

Table 21.8 Timing of On-Chip Supporting Modules

Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC,

VSS = AVSS = 0 V, φ = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications),

Ta = –40 to +85°C (wide-range specifications)

Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, Vref = 4.5 V to AVCC,

VSS = AVSS = 0 V, φ = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications),

Ta = –40 to +85°C (wide-range specifications)

Condition A

Condition B

Item

Symbol Min

Max

Min

Max

Unit

Test Conditions

PORT

Output data delay

time

tPWD

—

100

—

Figure 21.22

Input data setup

time

tPRS

—

Input data hold

time

tPRH

—

PPG

Pulse output delay

time

tPOD

—

100

—

Figure 21.23

TPU

Timer output delay

time

tTOCD

—

100

—

Figure 21.24

Timer input setup

time

tTICS

—

Timer clock input

setup time

tTCKS

—

Figure 21.25

Single

edge

tTCKWH

1.5

—

1.5

—

tcyc

Timer

clock

pulse

width

Both

edges

tTCKWL

2.5

—

2.5

—

WDT

Overflow output

delay time

tWOVD

—

100

—

Figure 21.26

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