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HD6432351 Datasheet(PDF) 761 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 761 Page - Renesas Technology Corp |
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761 / 1025 page ![]() Section 21 Electrical Characteristics Rev. 3.00 Sep 15, 2006 page 727 of 988 REJ09B0330-0300 Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions SCI Asynchro- nous tScyc 4 — 4 — tcyc Figure 21.27 Input clock cycle Synchro- nous 6 — 6 — Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 — 1.5 tcyc Input clock fall time tSCKf — 1.5 — 1.5 Transmit data delay time tTXD — 100 — 50 ns Figure 21.28 Receive data setup time (synchronous) tRXS 100 — 50 — ns Receive data hold time (synchronous) tRXH 100 — 50 — ns A/D converter Trigger input setup time tTRGS 50 — 30 — ns Figure 21.29 |
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