HD64F2149YV datasheet(518/1075 Pages) RENESAS

Part #	HD64F2149YV

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

518 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 490 of 1044

REJ09B0280-0300

Internal base

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit

Data sampling

timing

15 0

Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode

Thus the receive margin in asynchronous mode is given by equation (1) below.

M = 0.5 –

D – 0.5

– (L – 0.5)F –

(1 + F)

× 100%

.......... (1)

Where M: Receive margin (%)

N: Ratio of bit rate to clock (N = 16)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by

equation (2) below.

When D = 0.5 and F = 0,

M =

× 16

× 100%

= 46.875%

0.5 –

.......... (2)

However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in

system design.

HD64F2149YV Datasheet(PDF) 518 Page - Renesas Technology Corp