HD64F2149YV datasheet(639/1075 Pages) RENESAS

639 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 611 of 1044

REJ09B0280-0300

HICR0

Bit 6

LPC2E

Description

LPC channel 2 operation is disabled

(Initial value)

No address (H'0062, 66) matches for IDR2, ODR2, or STR2

LPC channel 2 operation is enabled

HICR0

Bit 5

LPC1E

Description

LPC channel 1 operation is disabled

(Initial value)

No address (H'0060, 64) matches for IDR1, ODR1, or STR1

LPC channel 1 operation is enabled

HICR0 Bit 4—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20

gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by

firmware operation of the P81 output.

When the fast A20 gate function is enabled, the DDR bit for P81 must not be set to 1.

HICR0

Bit 4

FGA20E

Description

Fast A20 gate function disabled

(Initial value)

• Other function of pin P81 is enabled

• GA20 output internal state is initialized to 1

Fast A20 gate function enabled

• GA20 pin output is open-drain (external V

CC pull-up resistor required)

HICR0 Bit 2—PME Output Enable (PMEE)

HICR1 Bit 2—PME Output Bit (PMEB)

These bits control PME output.

PME pin output is open-drain, and an external pull-up resistor is

needed to pull the output up to V

CC.

When the PME output function is used, the DDR bit for P80 must not be set to 1.

HD64F2149YV Datasheet(PDF) 639 Page - Renesas Technology Corp