R4S2426 datasheet(21/1302 Pages) RENESAS

21 / 1302 page

Rev. 1.00 Sep. 19, 2008 Page xxi of xxviii

12.4.6 Example of Non-Overlapping Pulse Output

(Example of Four-Phase Complementary Non-Overlapping Output) .................. 791

12.4.7 Inverted Pulse Output ........................................................................................... 793

12.4.8 Pulse Output Triggered by Input Capture ............................................................. 794

12.5

Usage Notes ....................................................................................................................... 795

12.5.1 Module Stop Mode Setting ................................................................................... 795

12.5.2 Operation of Pulse Output Pins............................................................................. 795

Section 13 8-Bit Timers (TMR).........................................................................797

13.1

Features.............................................................................................................................. 797

13.2

Input/Output Pins ...............................................................................................................799

13.3

Register Descriptions ......................................................................................................... 799

13.3.1 Timer Counter (TCNT)......................................................................................... 800

13.3.2 Time Constant Register A (TCORA).................................................................... 800

13.3.3 Time Constant Register B (TCORB) .................................................................... 800

13.3.4 Timer Control Register (TCR).............................................................................. 801

13.3.5 Timer Counter Control Register (TCCR) ............................................................. 802

13.3.6 Timer Control/Status Register (TCSR)................................................................. 804

13.4

Operation ........................................................................................................................... 808

13.4.1 Pulse Output.......................................................................................................... 808

13.4.2 Reset Input ............................................................................................................ 809

13.5

Operation Timing............................................................................................................... 810

13.5.1 TCNT Incrementation Timing .............................................................................. 810

13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 811

13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 812

13.5.4 Timing of Compare Match Clear .......................................................................... 812

13.5.5 Timing of TCNT External Reset........................................................................... 813

13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 813

13.6

Operation with Cascaded Connection................................................................................ 814

13.6.1 16-Bit Counter Mode ............................................................................................ 814

13.6.2 Compare Match Count Mode................................................................................ 814

13.7

Interrupt Sources................................................................................................................ 815

13.7.1 Interrupt Sources and DTC Activation ................................................................. 815

13.7.2 A/D Converter Activation..................................................................................... 815

13.8

Usage Notes ....................................................................................................................... 816

13.8.1 Contention between TCNT Write and Clear......................................................... 816

13.8.2 Contention between TCNT Write and Increment ................................................. 817

13.8.3 Contention between TCOR Write and Compare Match ....................................... 818

13.8.4 Contention between Compare Matches A and B .................................................. 819

13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 819

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