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M32C/86T Datasheet(PDF) 198 Page - Renesas Technology Corp |
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M32C/86T Datasheet(HTML) 198 Page - Renesas Technology Corp |
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198 / 505 page ![]() Page 175 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 16. Three-Phase Motor Control Timer Functions ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 16.2 INVC0 Register INV00 INV01 INV02 INV03 INV05 INV06 INV07 INV04 Function Three-Phase PWM Control Register 0(1) Bit Name Bit Symbol Symbol Address After Reset INVC0 030816 0016 RW RW RW RW RW RW RW RW RW Item INV06 = 0 INV06 = 1 Transfer trigger is generated when the INV07 bit is set to "1". Trigger to the dead time timer is also generated when setting the INV06 bit to "1". Its value is "0" when read. NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). Rewrite the INV02 to INV00 and INV06 bits when the timers A1,A2, A4 and B2 stop. 2. Set the INV01 bit to "1" after setting the ICTB2 register. 3. The INV01 and INV00 bit settings are enabled only when the INV11 bit in the INVC1 register is set to "1" (three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter underflows, regardless of INV01 and INV00bit settings, when the INV11 bit is set to "0" (three-phase mode). When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflows. When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. 4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2 counter. 5. Set pins after the INV02 bit is set to "1". See Table 16.2 for pin settings. 6. When the INV02 bit is set to "1" and the INV03 bit to "0", the U, U, V, V, W and W pins, including pins shared with other output functions, are all placed in high-impedance states. 7. The INV03 bit is set to "0" when the followings occurs : - Reset - A concurrent active state occurs while the INV04 bit is set to "1" - The INV03 bit is set to "0" by program - An "H" signal applied to the NMI pin changes to an "L" signal 8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0". 9. The following table describes how the INV06 bit setting works. Transfer trigger : Timer B2 counter underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1 0: The ICTB2 counter is incremented by one on the rising edge of the timer A1 reload control signal 1: The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 0: ICTB2 counter is incremented by one when timer B2 counter underflows 1: Selected by the INV00 bit 10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). Transferred once by generating a transfer trigger after setting the IDB0 and IDB1 registers Interrupt Enable Output Polarity Select Bit(3) Interrupt Enable Output Specification Bit(2, 3) Mode Select Bit (4, 5, 6) 0: No three-phase control timer function 1: Three-phase control timer function 0: Disables three-phase control timer output 1: Enables three-phase control timer output Output Control Bit (6, 7) 0: Enables concurrent active output 1: Disables concurrent active output Positive and Negative- Phases Concurrent Active Disable Function Enable Bit Positive and Negative- Phases Concurrent Active Output Detect Flag(8) 0: Not detected 1: Detected Modulation Mode Select(9, 10) 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Software Trigger Select Transferred every time a transfer trigger is generated By a transfer trigger, or the falling edge of a one-shot pulse of the timer A1, A2 or A4 On the falling edge of a one-shot pulse of the timer A1, A2 or A4 Timing to Trigger the Dead Time Timer when the INV16 Bit=0 INV13 Bit Enabled when the INV11 bit=1 and the INV06 bit=0 Disabled Timing to Transfer from the IDB0 and IDB1 Registers to Three- Phase Output Shift Register Mode Triangular wave modulation mode Sawtooth wave modulation mode b7 b6 b5 b4 b3 b2 b1 b0 |
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