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M32C/86T Datasheet(PDF) 199 Page - Renesas Technology Corp |
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M32C/86T Datasheet(HTML) 199 Page - Renesas Technology Corp |
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199 / 505 page ![]() Page 176 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 16. Three-Phase Motor Control Timer Functions ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M INV10 INV11 INV12 INV13 INV15 INV14 Function Three-Phase PWM Control Register 1(1) Timer A1, A2 and A4 Start Trigger Select Bit Carrier Wave Detect Flag(4) Dead Time Timer Trigger Select Bit Output Polarity Control Bit 0: Timer A1 reload control signal is "0" 1: Timer A1 reload control signal is "1" Timer A1-1, A2-1 and A4-1 Control Bit(2, 3) 0: Three-phase mode 0 1: Three-phase mode 1 Dead Time Timer Count Source Select Bit 0 : f1 1 : f1 divided-by-2 0: Timer B2 counter underflows 1: Timer B2 counter underflows and write to the TB2 register 0 : Active "L" of an output waveform 1 : Active "H" of an output waveform Dead Time Disable Bit 0: Enables dead time 1: Disables dead time Bit Name Bit Symbol Symbol Address After Reset INVC1 030916 0016 RW RW RW RW RO RW RW RW Reserved Bit Set to "0" RW NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). The timers A1, A2, A4, and B2 must be stopped during rewrite. 2. The following table lists how the INV11 bit setting works. 3. When the INV06 bit in the INVC0 registser is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0". Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (Timer B2 counter underflows). 4. The INV13 bit setting is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the INV11 bit to "1". 5. If the following conditions are all met, set the INV16 bit to "1". • The INV15 bit is set to "0" • The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit in the INVC0 register is set to "1". (The positive-phase and negative-phase outputs always provide opposite level signals.) If the above conditions are not met, set the INV16 bit to "0". 0: Falling edge of a one-shot pulse of the timer A1, A2 and A4(5) 1: Rising edge of the three-phase output shift register (U-, V-, W-phase) INV16 (b7) b7 b6 b5 b4 b3 b2 b1 b0 TA11, TA21 and TA41 Registers Not used Used INV13 Bit Disabled Enabled Item Mode INV11 = 0 INV11 = 1 Three-phase mode 0 Three-phase mode 1 Disabled. The ICTB2 counter is incremented whenever the timer B2 counter underflows Enabled when INV11=1 and INV06=0 0 INV01 and INV00 Bit in the INVC0 Register Figure 16.3 INVC1 Register |
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