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M32C/86T Datasheet(PDF) 207 Page - Renesas Technology Corp |
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M32C/86T Datasheet(HTML) 207 Page - Renesas Technology Corp |
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207 / 505 page  Page 184 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M m : setting value of UiBRG register RxDi Receive Control Circuit Transmit Control Circuit 1 / (m+1) 1/16 1/16 1/2 UiBRG Register Clock Synchronous (when internal clock is selected) Clock Asynchronous Receive Clock Synchronous Clock Synchronous Clock Synchronous (when internal clock is selected) Clock Synchronous (when external clock is selected) Receive Clock Transmit Clock CLKi CTSi / RTSi f1 f8 f2n(2) VSS CTSi TxDi RxD Polarity Switching Circuit TxD Polarity Switching Circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK Polarity Switching Circuit CKDIR Internal External Selecting Clock Source Transmit/ Receive Unit (Note 1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 01 10 0 00 1 CKPOL CLK1 and CLK0 010, 100, 101, 110 010, 100, 101, 110 001 001 Clock Asynchronous Transmit SMD2 to SMD0 CKDIR CRD CRD 1 1 0 0 RTSi CRS 0 1 8-bit Clock Asynchronous Clock Synchronous 7-bit Clock Asynchronous SP SP PAR Clock Synchronous Clock Synchronous Low-order bits of data bus TxDi UARTi Transmit Register PAR disabled PAR enabled D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB Register Clock Synchronous UiRB Register UARTi Receive Register 2SP 1SP RxDi D7 D6 D5 D4 D3 D2 D1 D0 D8 000 0 000 SP SP PAR 0 Inverse No inverse Error Signal Output Circuit RxD Data Inverse Circuit Error Signal Output enable Error Signal Output disable Inverse No inverse Logic Inverse Circuit + MSB/LSB Conversion Circuit Logic Inverse Circuit + MSB/LSB Conversion Circuit PAR enabled PAR disabled Clock Synchronous TxD Data Inverse Circuit SP: Stop bit PAR: Parity bit i=0 to 4 SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in the UiMR register CLK1 and CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register UiERE: Bit in the UiC1 register 0 1 IOPOL 1 0 PRYE 0 1 9-bit Clock Asynchronous Clock Synchronous 8-bit Clock Asynchronous Clock Asynchronous 9-bit Clock Asynchronous Type 7-bit Clock Asynchronous 0 1 1 1 SMD2 to SMD0 STPS 0 7-bit Clock Asynchronous 8-bit Clock Asynchronous 8-bit Clock Asynchronous 9-bit Clock Asynchronous 7-bit Clock Asynchronous 1SP 2SP 0 1 STPS PRYE 0 1 Clock Asynchronous 1 9-bit Clock Asynchronous 11 00 0 0 1 1 IOPOL UiERE High-order bits of data bus SMD2 to SMD0 Figure 17.1 UARTi Block Diagram |
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