H8SXSLASH1525R datasheet(17/826 Pages) RENESAS

17 / 826 page

Rev. 1.00 Mar. 06, 2006 Page xvii of xxxviii

12.9.1 Module Stop Mode Setting ................................................................................... 443

12.9.2 Break Detection and Processing ........................................................................... 443

12.9.3 Mark State and Break Detection ........................................................................... 443

12.9.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ..................................................................... 443

12.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 444

12.9.6 Restrictions on Using DMAC ............................................................................... 444

12.9.7 SCI Operations during Mode Transitions ............................................................. 445

Section 13 Controller Area Network (RCAN-ET) ............................................449

13.1

Summary............................................................................................................................ 449

13.1.1 Overview............................................................................................................... 449

13.1.2 Scope..................................................................................................................... 449

13.1.3 Audience ............................................................................................................... 449

13.1.4 References............................................................................................................. 450

13.1.5 Features................................................................................................................. 450

13.2

Architecture ....................................................................................................................... 451

13.2.1 Block Diagram...................................................................................................... 451

13.2.2 Important............................................................................................................... 452

13.2.3 Input/Output Pins .................................................................................................. 453

13.2.4 Memory Map ........................................................................................................ 454

13.3

Mailbox.............................................................................................................................. 455

13.3.1 Mailbox Structure ................................................................................................. 455

13.3.2 Message Control Field .......................................................................................... 457

13.3.3 Local Acceptance Filter Mask (LAFM)................................................................ 461

13.3.4 Message Data Fields ............................................................................................. 462

13.4

RCAN-ET Control Registers ............................................................................................. 463

13.4.1 Master Control Register (MCR) ........................................................................... 463

13.4.2 General Status Register (GSR) ............................................................................. 469

13.4.3 Bit Configuration Register (BCR0, BCR1) .......................................................... 471

13.4.4 Interrupt Request Register (IRR) .......................................................................... 476

13.4.5 Interrupt Mask Register (IMR) ............................................................................. 483

13.4.6 Transmit Error Counter (TEC) and Receive Error Counter (REC)....................... 484

13.5

RCAN-ET Mailbox Registers ............................................................................................ 485

13.5.1 Transmit Pending Register (TXPR0, TXPR1)...................................................... 486

13.5.2 Transmit Cancel Register (TXCR0) ..................................................................... 489

13.5.3 Transmit Acknowledge Register0 (TXACK0) ..................................................... 490

13.5.4 Abort Acknowledge Register0 (ABACK0) .......................................................... 491

13.5.5 Data Frame Receive Pending Register0 (RXPR0)................................................ 492

13.5.6 Remote Frame Receive Pending Register0 (RFPR0) ........................................... 493

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