R8C23 datasheet(93/549 Pages) RENESAS

93 / 549 page

R8C/22 Group, R8C/23 Group

10. Clock Generation Circuit

Rev.2.00 Aug 20, 2008

Page 73 of 501

REJ09B0251-0200

Figure 10.2

CM0 Register

System Clock Control Register 0

(1)

Symbol

Address

After Reset

CM0

0006h

01101000b

Bit Symbol

Bit Name

Function

NOTES:

b7 b6 b5 b4 b3 b2 b1 b0

00 1

0 0

—

(b1-b0)

Reserved bits

Set to 0

CM02

WAIT peripheral function clock stop

bit

0 : Peripheral function clock does not stop

in w ait mode

1 : Peripheral function clock stops in w ait

mode

—

(b3)

Reserved bit

Set to 1

—

(b4)

Reserved bit

Set to 0

CM05

XIN clock (XIN-XOUT) stop bit(2,4)

0 : XIN clock oscillates

1 : XIN clock stops(3)

CM06

System clock division select bit 0(5)

0 : Enables CM16, CM17

1 : Divide-by-8 mode

—

(b7)

Reserved bit

Set to 0

When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM0 register.

The CM05 bit is to stop the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator

mode is selected. Do not use this bit for w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the

follow ing orders:

(a) Set the OCD0 and OCD1 bits in the OCD register to 00b.

(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).

During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.

P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the

CM1 register is set to 0 (P4_6, P4_7).

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