HD64F3039F datasheet(13/708 Pages) RENESAS

13 / 708 page

Rev.3.00 Mar. 26, 2007 Page xiii of xxii

REJ09B0353-0300

5.1.3

Pin Configuration................................................................................................. 85

5.1.4

5.2

Register Descriptions ........................................................................................................86

5.2.1

System Control Register (SYSCR) ...................................................................... 86

5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 88

5.2.3

IRQ Status Register (ISR).................................................................................... 93

5.2.4

IRQ Enable Register (IER) .................................................................................. 94

5.2.5

IRQ Sense Control Register (ISCR) .................................................................... 95

5.3

Interrupt Sources ............................................................................................................... 96

5.3.1

External Interrupts ............................................................................................... 96

5.3.2

Internal Interrupts................................................................................................. 97

5.3.3

Interrupt Vector Table.......................................................................................... 97

5.4

Interrupt Operation............................................................................................................ 100

5.4.1

Interrupt Handling Process................................................................................... 100

5.4.2

Interrupt Sequence ............................................................................................... 105

5.4.3

Interrupt Response Time...................................................................................... 106

5.5

Usage Notes ...................................................................................................................... 107

5.5.1

Contention between Interrupt and Interrupt-Disabling Instruction ...................... 107

5.5.2

Instructions that Inhibit Interrupts........................................................................ 108

5.5.3

Interrupts during EEPMOV Instruction Execution .............................................. 108

5.5.4

Usage Notes ......................................................................................................... 108

Section 6 Bus Controller.................................................................................................... 111

6.1

Overview........................................................................................................................... 111

6.1.1

Features ................................................................................................................ 111

6.1.2

Block Diagram ..................................................................................................... 112

6.1.3

Input/Output Pins ................................................................................................. 113

6.1.4

6.2

Register Descriptions ........................................................................................................ 114

6.2.1

Access State Control Register (ASTCR) ............................................................. 114

6.2.2

Wait Control Register (WCR).............................................................................. 115

6.2.3

Wait State Controller Enable Register (WCER) .................................................. 116

6.2.4

Address Control Register (ADRCR).................................................................... 117

6.3

Operation........................................................................................................................... 119

6.3.1

Area Division ....................................................................................................... 119

6.3.2

Bus Control Signal Timing .................................................................................. 121

6.3.3

Wait Modes.......................................................................................................... 123

6.3.4

Interconnections with Memory (Example) .......................................................... 129

6.4

Usage Notes ...................................................................................................................... 131

6.4.1

6.4.2

Precautions on Setting ASTCR and ABWCR...................................................... 131

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