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H83724 Datasheet(PDF) 86 Page - Renesas Technology Corp |
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H83724 Datasheet(HTML) 86 Page - Renesas Technology Corp |
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86 / 352 page  Rev. 3.00, 12/94, page 71 of 334 3.2.5 Internal Interrupts There are ten internal interrupts that can be raised by the on-chip peripheral modules. These interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted and an interrupt handler is executed, the I bit is set to 1. On the order of priority of interrupts from on-chip peripheral modules, see table 3-2. 3.2.6 Operations When an Interrupt is Raised Interrupts are controlled by an interrupt controller. Figure 3-2 gives a block diagram of this interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance. Figure 3-2 Block Diagram of Interrupt Controller Interrupt controller Interrupt request CCR (CPU) I IRQ to IRQ interrupt request flag or internal interrupt request flag 50 IRQ to IRQ interrupt request flag or internal interrupt enable flag 50 |
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