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H83814 Datasheet(PDF) 86 Page - Renesas Technology Corp |
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H83814 Datasheet(HTML) 86 Page - Renesas Technology Corp |
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86 / 456 page ![]() Bit 5: Reserved bit Bit 5 is reserved; it is always read as 0, and cannot be modified. Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG Description 0 Clearing conditions: (initial value) When IRRTG = 1, it is cleared by writing 0 1 Setting conditions: When pin TMIG is set to TMIG input and the designated signal edge is detected Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH Description 0 Clearing conditions: (initial value) When IRRTFH = 1, it is cleared by writing 0 1 Setting conditions: When counter FH matches output compare register FH in 8-bit timer mode, or when 16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL, OCRFH) in 16-bit timer mode Bit 2: Timer FL interrupt request flag (IRRTFL) Bit 2 IRRTFL Description 0 Clearing conditions: (initial value) When IRRTFL = 1, it is cleared by writing 0 1 Setting conditions: When counter FL matches output compare register FL in 8-bit timer mode Bit 1, 0: Reserved bits Bit 1, 0 are reserved; they are always read as 0, and cannot be modified. 73 |
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