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SH7751R Datasheet(PDF) 21 Page - Renesas Technology Corp |
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SH7751R Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 1224 page  Rev.4.00 Oct. 10, 2008 Page xxi of xcviii REJ09B0370-0400 Item Page Revision (See Manual for Details) 12.2.7 Input Capture Register 2 (TCPR2) 326 Title amended 12.4 Interrupts 332 Description amended There are six TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on channels 0 to 4, and input capture interrupts on channel 2 only. 12.5.4 External Clock Frequency 333 Description amended Ensure that the external clock frequency for any channel does not exceed Pck/8. 13.1.4 Register Configuration Table 13.2 BSC Registers 340 Table amended Name Abbrevia- tion R/W Initial Value Bus control register 3* 2 BCR3 R/W H'0001 13.1.6 PCMCIA Support Table 13.5 PCMCIA Support Interfaces 347 Table and notes amended Pin Corresponding LSI Pin 57 — 58 Output from port 59 RDY*2 Notes: 1. WP is not supported. 2. Input an external wait request with correct polarity. 13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only) 359 Description amended BCR3 is initialized to H'0001 by a power-on reset, but is not initialized by a manual reset or in standby mode. 13.2.7 Wait Control Register 3 (WCR3) 375 Description amended of Bits 4n+3 Bits 4n+3 ⎯Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in the SH7751R): When reading, these bits specify the timing for the negation of read strobe. These bits should be cleared to 0 when a byte control SRAM setting is made. Valid only for the SRAM interface. gate Bit 4n + 3: AnRDH Read-Strobe Ne Timing 0 Read strobe negated after hold wait cycles specified by WCR3.AnH bits (Initial value) 1 Read strobe negated according to data sampling timing Note: n = 4 or 1 |
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