3819 datasheet(10/218 Pages) RENESAS

10 / 218 page

3819 Group USER’S MANUAL

Table of contents

Fig. 43 Timing of noise filter circuit ..................................................................................................... 45

Fig. 44 Example of reset circuit ........................................................................................................... 46

Fig. 45 Reset sequence ........................................................................................................................ 46

Fig. 46 Internal state at reset ............................................................................................................... 47

Fig. 47 Ceramic resonator external circuit ......................................................................................... 48

Fig. 48 External clock input circuit ...................................................................................................... 48

Fig. 49 Clock generating circuit block diagram ................................................................................. 49

Fig. 50 State transition of system clock ............................................................................................. 50

Fig. 51 Programming and testing of One Time PROM version ...................................................... 52

Fig. 52 Zero cross detection input characteristics ............................................................................ 57

Fig. 53 Circuit for measuring output switching characteristics ........................................................ 58

Fig. 54 Power source current characteristic example ....................................................................... 60

Fig. 55 Power source current characteristic example (in wait mode) ............................................ 60

Fig. 56 Standard characteristic example of High-breakdown-voltage P-channel open-drain output port .................. 61

Fig. 57 Standard characteristic example of CMOS output port at P-channel drive ..................... 61

Fig. 58 Standard characteristic example of CMOS output port at N-channel drive ..................... 62

Fig. 59 A-D conversion standard characteristics ............................................................................... 63

Fig. 60 D-A conversion standard characteristics ............................................................................... 64

Fig. 61 Timing chart after an interrupt occurs ................................................................................... 66

Fig. 62 Time up to execution of the interrupt processing routine .................................................. 66

Fig. 63 A-D conversion equivalent circuit ........................................................................................... 68

Fig. 64 A-D conversion timing chart .................................................................................................... 68

CHAPTER 2. APPLICATION

Fig. 2.1.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B) ............................................ 70

Fig. 2.1.2 Structure of Port P2 direction register .............................................................................. 70

Fig. 2.1.3 Structure of Port Pi direction register (i = 4, 5, 6, 7, 8, A, B) ..................................... 71

Fig. 2.2.1 Structure of Timer i (i = 1, 3, 4, 5, 6) .............................................................................. 72

Fig. 2.2.2 Structure of Timer 2 ............................................................................................................. 72

Fig. 2.2.3 Structure of Timer 6 PWM register ................................................................................... 73

Fig. 2.2.4 Structure of Timer 12 mode register ................................................................................. 73

Fig. 2.2.5 Structure of Timer 34 mode register ................................................................................. 74

Fig. 2.2.6 Structure of Timer 56 mode register ................................................................................. 74

Fig. 2.2.7 Structure of Interrupt request register 1 ........................................................................... 75

Fig. 2.2.8 Structure of Interrupt request register 2 ........................................................................... 75

Fig. 2.2.9 Structure of Interrupt control register 1 ............................................................................ 76

Fig. 2.2.10 Structure of Interrupt control register 2 .......................................................................... 76

Fig. 2.2.11 Connection of timers and setting of division ratios [Clock function] .......................... 78

Fig. 2.2.12 Setting of related registers (1) [Clock function] ............................................................. 78

Fig. 2.2.13 Setting of related registers (2) [Clock function] ............................................................. 79

Fig. 2.2.14 Control procedure [Clock function] .................................................................................. 80

Fig. 2.2.15 Example of a peripheral circuit ........................................................................................ 81

Fig. 2.2.16 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] .... 81

Fig. 2.2.17 Setting of related registers [Piezoelectric buzzer output] ............................................. 82

Fig. 2.2.18 Control procedure [Piezoelectric buzzer output] ............................................................ 82

Fig. 2.2.19 A method for judging if Video synchronization signal exists ....................................... 83

Fig. 2.2.20 Setting of related registers [Measurement of frequency] ............................................. 84

Fig. 2.2.21 Control procedure [Measurement of frequency] ............................................................. 85

Fig. 2.3.1 Structure of Serial I/O automatic transfer data pointer .................................................. 86

Fig. 2.3.2 Structure of Serial I/O 1 control register .......................................................................... 86

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