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R8C33A Datasheet(PDF) 73 Page - Renesas Technology Corp |
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R8C33A Datasheet(HTML) 73 Page - Renesas Technology Corp |
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73 / 617 page ![]() R8C/33A Group 6. Voltage Detection Circuit REJ09B0455-0010 Rev.0.10 Feb 29, 2008 Page 45 of 586 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) Note: 1. The VW0C0 bit is enabled when the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disabled) when the VCA25 bit in the VCA2 register is set to 0 (voltage detection 0 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure in Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset . Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW0C register. Address 0038h Bit b7b6 b5b4b3b2 b1 b0 Symbol — — VW0F1 VW0F0 — — VW0C1 VW0C0 After Reset The LVDAS bit in the OFS register is set to 1. 1 100 X 010 After Reset The LVDAS bit in the OFS register is set to 0. 1 100 X 011 Bit Symbol Bit Name Function R/W b0 VW0C0 Voltage monitor 0 reset enable bit (1) 0: Disabled 1: Enabled R/W b1 VW0C1 Voltage monitor 0 digital filter disabled mode select bit 0: Digital filter enabled mode (digital filter circuit enabled) 1: Digital filter disabled mode (digital filter circuit disabled) R/W b2 — Reserved bit Set to 0. R/W b3 — Reserved bit When read, the content is undefined. R b4 VW0F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW0F1 R/W b6 — Reserved bits Set to 1. R/W b7 — R/W |
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