M16CSLASH62 datasheet(396/621 Pages) RENESAS

396 / 621 page

SI/O3, 4

Mitsubishi microcomputers

M16C / 62 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

381

Figure 2.6.4. Set-up procedure of transmission in SI/O3, 4 mode

Setting SI/Oi transmit/receive control register (i=3, 4)

SI/Oi transmit/receive control register (i=3,4) [Address 036216, 036616]

SiC(i=3,4)

Synchronous clock select bit

1 : Internal clock

Internal synchronous clock select bit

0 0 : f1 is selected

0 1 : f8 is selected

1 0 : f32 is selected

1 1 : Inhibited

b1 b0

SOUTi output disable bit

0 : SOUTi output

SI/Oi port select bit

1 : SOUTi output, CLK function

Transfer format select bit

0 : LSB first

Note 1: Be sure to set the protect register and SI/Oi control register successively.

Clearing the protect (set to write-enabled state)

Protect register [Address 000A16]

PRCR

Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716

)

0 : Write-inhibited

1 : Write-enabled

Enables writing to port P9 direction register (address 03F316) and SI/Oi control register

(i=3,4) (addresses 036216 and 036616)

1 : Write-enabled

SOUTi initial value set bit(Effective when SMi3=0)

0 : L output

1 : H output

Setting SI/Oi bit rate generator (i = 3, 4)

SI/Oi bit rate generator (i = 3, 4) [Address 036316, 036716]

SiBRG (i = 3, 4)

Can be set to 0016 to FF16 (Note 2)

Note 2: Write to SI/Oi bit rate generator when transmission/reception is halted.

Writing transmit data

SI/Oi transmit/receive register (i=3, 4) [Address 036016, 036416]

SiTRR (i=3, 4)

Setting transmission data (Note 3)

Note 3: Write to SI/Oi transmit/receive register when transmission/reception is halted.

SI/Oi interrupt

request bit

Reading Receive data

SI/Oi transmit/receive register (i=3, 4) [Address 036016, 036416]

SiTRR (i=3, 4)

Receive data

Transfer the next data

Wait for a 1/2 transfer clock period

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