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SH7730 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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SH7730 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 1188 page ![]() Rev. 1.00 Sep. 19, 2007 Page xxxix of xlviii Figure 33.18 Burst Read Bus Cycle of SDRAM (Single Read × 8) (Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 2 Cycles) .......................................... 1078 Figure 33.19 Burst Read Bus Cycle of SDRAM (Single Read × 8) (Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycles, TRP = 1 Cycle) .......................................... 1079 Figure 33.20 Single Write Bus Cycle of SDRAM (Auto Precharge Mode, TRWL = 1 Cycle) ......................................................... 1080 Figure 33.21 Single Write Bus Cycle of SDRAM (Auto Precharge Mode, TRCD = 3 Cycles, TRWL = 1 Cycle)................................................................. 1081 Figure 33.22 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) ....................................................... 1082 Figure 33.23 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Auto Precharge Mode, TRCD = 2 Cycles, TRWL = 1 Cycle)...................................................... 1083 Figure 33.24 Burst Read Bus Cycle of SDRAM (Single Read × 8) (Bank Active Mode: ACTV + READ Command, CAS Latency 2, TRCD = 1 Cycle) ........................ 1084 Figure 33.25 Burst Read Bus Cycle of SDRAM (Single Read × 8) (Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, TRCD = 1 Cycle) ...... 1085 Figure 33.26 Burst Read Bus Cycle of SDRAM (Single Read × 8) (Bank Active Mode: PRE + ACTV + READ Command, Different Row Address, CAS Latency 2, TRCD = 1 Cycle) ................................................................................................ 1086 Figure 33.27 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) ................................................... 1087 Figure 33.28 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) ................................................... 1088 Figure 33.29 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Bank Active Mode: PRE + ACTV + WRIT Command, TRCD = 1 Cycle)........................................ 1089 Figure 33.30 Auto Refresh Timing of SDRAM (TRP = 2 Cycles) .......................................... 1090 Figure 33.31 Self Refresh Timing of SDRAM (TRP = 2 Cycles) ............................................ 1091 Figure 33.32 Power-On Sequence of SDRAM (Mode Write Timing, TRP = 2 Cycles) .......... 1092 Figure 33.33 Write-to-Read Bus Cycle in Power-Down Mode of SDRAM (Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle).................................................................................................................. 1093 Figure 33.34 Read-to-Write Bus Cycle in Power-Down Mode of SDRAM (Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle).................................................................................................................. 1094 Figure 33.35 PCMCIA Memory Card Interface Bus Timing ................................................... 1095 Figure 33.36 PCMCIA Memory Card Interface Bus Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait 1, Hardware Wait 1)................................... 1096 Figure 33.37 PCMCIA I/O Card Interface Bus Timing............................................................ 1097 Figure 33.38 PCMCIA I/O Card Interface Bus Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait 1, Hardware Wait 1)................................... 1098 |
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