H83029 datasheet(21/1010 Pages) RENESAS

21 / 1010 page

Rev. 2.0, 06/04, page xviii of xxiv

10.4.6 Input Capture Setting ........................................................................................... 402

10.5

Interrupt ............................................................................................................................ 403

10.5.1 Interrupt Sources.................................................................................................. 403

10.5.2 A/D Converter Activation.................................................................................... 404

10.6

8-Bit Timer Application Example..................................................................................... 404

10.7

Usage Notes ...................................................................................................................... 405

10.7.1 Contention between 8TCNT Write and Clear...................................................... 405

10.7.2 Contention between 8TCNT Write and Increment .............................................. 406

10.7.3 Contention between TCOR Write and Compare Match ...................................... 407

10.7.4 Contention between TCOR Read and Input Capture ........................................... 408

10.7.5 Contention between Counter Clearing by Input Capture and

Counter Increment ............................................................................................... 409

10.7.6 Contention between TCOR Write and Input Capture .......................................... 410

10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection) ........................................................................................ 411

10.7.8 Contention between Compare Matches A and B ................................................. 412

10.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 412

Section 11 Programmable Timing Pattern Controller (TPC) ............................415

11.1

Overview........................................................................................................................... 415

11.1.1 Features................................................................................................................ 415

11.1.2 Block Diagram ..................................................................................................... 416

11.1.3 TPC Pins .............................................................................................................. 417

11.1.4 Registers............................................................................................................... 418

11.2

Register Descriptions ........................................................................................................ 419

11.2.1 Port A Data Direction Register (PADDR) ........................................................... 419

11.2.2 Port A Data Register (PADR) .............................................................................. 419

11.2.3 Port B Data Direction Register (PBDDR)............................................................ 420

11.2.4 Port B Data Register (PBDR) .............................................................................. 420

11.2.5 Next Data Register A (NDRA) ............................................................................ 421

11.2.6 Next Data Register B (NDRB)............................................................................. 423

11.2.7 Next Data Enable Register A (NDERA).............................................................. 425

11.2.8 Next Data Enable Register B (NDERB) .............................................................. 426

11.2.9 TPC Output Control Register (TPCR) ................................................................. 427

11.2.10 TPC Output Mode Register (TPMR) ................................................................... 430

11.3

Operation .......................................................................................................................... 432

11.3.1 Overview.............................................................................................................. 432

11.3.2 Output Timing...................................................................................................... 433

11.3.3 Normal TPC Output............................................................................................. 434

11.3.4 Non-Overlapping TPC Output ............................................................................. 436

11.3.5 TPC Output Triggering by Input Capture ............................................................ 438

11.4

Usage Notes ...................................................................................................................... 439

11.4.1 Operation of TPC Output Pins ............................................................................. 439

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