7470_M datasheet(86/361 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.12 Timers

[Setting method]

1 The count operation of a timer to be used is stopped.

Refer to “Table 1.12.2 Setting for count stop.”

2 Port P13 is put into the output mode by setting bit 3 of the port P1 direction register (address

00C116) to “1.”

3 Select a count source of Timer 3 and Timer 4. However, don't select the Timer 3 overflow signal

as a count source of Timer 4.

Refer to “Table 1.12.5 Setting for Timer 3 count source” and “Table 1.12.6 Setting for Timer

4 count source.”

4 Set the bit 7 of the Timer 34 mode register to “1.”

5 Set a value in the timer.

Refer to “Table 1.12.7 Address allocation of timer.”

6 Set the bit 7 of the Timer mode register 2 to “1.”

7 The count operation of a timer to be used is started.

Refer to “Table 1.12.8 Count start setting.”

Note: When the PWM mode is started from another mode, the PWM waveform starts with the “L”

state.

1.12.3 Input latch function

There is a function which latches the levels of the INT0, INT1, CNTR0 and CNTR1 pins to the input latch

moment when a Timer 4 overflow occurs. The polarity of each pin is selected by the edge polarity

selection register, the level or the reverse level of each pin are latched to the Input latch register.

Table 1.12.13 shows the Edge polarity selection register setting related to the input latch.

Table 1.12.13 Edge polarity selection register setting

Latched contents

INT0 pin level

Reverse level on INT0 pin

INT1 pin level

Reverse level on INT1 pin

CNTR0 pin level

Reverse level on CNTR0 pin

CNTR1 pin level

Reverse level on CNTR1 pin

Input latch register

(ILR: Address 00D616)

Edge polarity selection register

(EG: Address 00D416)

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7470_M Datasheet(PDF) 86 Page - Renesas Technology Corp