H83318 datasheet(86/574 Pages) RENESAS

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IRQ Enable Register (IER)

Bit

76543210

IRQ7E

IRQ6E

IRQ5E

IRQ4E

IRQ3E

IRQ2E

IRQ1E

IRQ0E

Initial value

00000000

Read/Write

R/W

Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ7

to IRQ0 interrupts individually.

Bits 7 to 0

IRQ7E to IRQ0E

Description

IRQ

7 to IRQ 0 interrupt requests are disabled

(Initial state)

IRQ

7 to IRQ 0 interrupt requests are enabled

When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an

interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to

IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit

(IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is

cleared to 0 while the request is still pending, the request will remain pending, although new

requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the

interrupt-handling routine can be executed even though the enable bit is now 0.

If execution of interrupt-handling routines under these conditions is not desired, it can be avoided

by using the following procedure to disable and clear interrupt requests.

1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically

when execution jumps to an interrupt vector.

2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests.

3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn

interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.

H83318 Datasheet(PDF) 86 Page - Renesas Technology Corp