7480_M datasheet(73/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-56

HARDWARE

1.11 Interrupts

1.11.7 Notes on Usage

Pay attention to the following notes when an interrupt is used.

(1)

For All Interrupts

Before the execution of an interrupt, set the corresponding interrupt request bit and interrupt enable

bit in the following order:

Clear the interrupt request bit to ‘0’ (no interrupt request).

Set the corresponding interrupt enable bit to ‘1’ (interrupt enabled).

The interrupt request bits can be changed by software, but retain the values immediately after a

rewrite instruction is executed. Therefore, the following operations must be performed after one or

more instructions at the completion of a rewrite instruction:

• Execute the BBC or BBS instruction after an interrupt request bit is changed.

• Set an interrupt enable bit to ‘1’ after an interrupt request bit is changed.

(2)

For the INT and CNTR Interrupts

When edge selection bits of the edge polarity selection register are set, interrupt request bits may

become ‘1’. Therefore, set edge selection bits in the following sequence:

Clear interrupt enable bit to ‘0’ (interrupt disabled).

Set edge selection bit.

Clear interrupt request bit to ‘0’ (no interrupt request).

Execute one or more instructions (NOP etc.).

Set interrupt enable bit to ‘1’ (interrupt enabled).

The INT0, INT1, CNTR0, and CNTR1 pins have the alternative functions of input port pins P30, P31,

I/O port pins P40, and P41, respectively. When these pins are used as input port pins, valid edges

can still be detected because the 7480 Group and 7481 Group does not have the function to switch

the INT and CNTR pins to input port pins. Therefore, when these pins are used as input port pins,

clear all the corresponding interrupt enable bits of the INT and CNTR interrupts to ‘0’ (disabled).

Keep the trigger width input to the INT pins 250 ns or more.

(3)

For the Key-On Wakeup Interrupt

When the key-on wakeup interrupt is used, execute the STP/WIT instruction after all inputs to port

P0 are held HIGH.

In states other than the stop/wait mode, the key-on wakeup interrupt is invalid.

(4)

For the BRK instruction interrupt

When the BRK instruction is executed, 2 is added to the contents of program counter, and then the

contents of the program counter are pushed onto the stack. As a result, upon return from the BRK

instruction interrupt service routine, the one byte subsequent to the BRK instruction is not executed.

Therefore, at programming, it is necessary to insert the NOP instruction immediately after the BRK

instruction.

When there are two or more interrupt sources of which interrupt request bits and interrupt enable bits

are ‘1’, but the interrupt disable flag is ‘1’ (that is, in the interrupt disabled state), the execution of

the BRK instruction starts execution of the interrupt service routine at the vector address with the

highest priority level in these sources.

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