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L9826 Datasheet(PDF) 9 Page - STMicroelectronics |
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L9826 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 17 page  L9826 3 Electrical Specifications CD00002120 9/17 fclk Clock frequency 50% duty cycle 3 MHz tclh Minimum time CLK = HIGH 160 ns tcll Minimum time CLK = LOW 160 ns tpcld Propagation delay CLK to data at SDO valid 4,9V ≤ V CC ≤ 5,1V 100 ns tcsdv NCS = LOW to data at SDO active 100 ns tsclch CLK low before NCS low Setup time CLK to NCS change H/L 100 ns thclcl CLK change L/H after NCS = low 100 ns tscld SDI input setup time CLK change H/L after SDI data valid 20 ns thcld SDI input hold time SDI data hold after CLK change H/L 20 ns tsclcl CLK low before NCS high 150 ns thclch CLK high after NCS high 150 ns tpchdz NCS L/H to output data float 100 ns NCS pulse filter time Multiple of 8 CLK cycles inside NCS period Table 4. Electrical Characteristcs (continued) (4.5V ≤ V CC ≤ 5,5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified). Symbol Parameter Test Condition Min. Typ. Max. Unit |
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