SUB ADDRESS

LSB

MSB

LSB

MSB

LSB

MSB

VPEAK

(V)

D94AU188

20

DEVIATION(KHz)

0.9

1.2

2.0

2.8

DETECTOR OFF (00)

32.5

45

75

OVM=01

OVM=10

OVM=11

Figure 4: Behaviour of the Deviation Dependent Threshold Adjust (Over Deviation Detector)

I

Interface Protocol

The interface protocol comprises:

A start condition (s)

A chip address byte, (the LSB bit determines

read/write transmission).

A subaddress byte

A sequence of data (N-bytes + acknowledge)

A stop condition (P)

S

1

00010

0 R/W ACK X

X

T

I

DATA

ACK P

ACK = Acknowledge

S = Start

P = Stop

I = Autoincrement

MAX CLOCK SPEED 500kbits/s

Autoincrement

If bit I in the subaddress byte is set to ”1”, the autoincrement of subaddress is enabled.

CHIP ADDRESS

DATA 1...DATA n

2.4V(11)

TRIG. THRESHOLD

0.9V

VPEAK

E’

D94AU187B

1.9V(10)

1.3V(01)

MONO

STEREO

noisy signal

good signal

ATC_SB OFF (00)

NOISE

3G

Figure 3: Behaviour of the Field Strength Controlled Threshold Adjustment

TDA7420

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