TDA7448

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SOFTWARE SPECIFICATION

Interface Protocol

The interface protocol comprises:

s

A start condition (S)

s

A chip address byte, containing the TDA7448 address

s

A subaddress bytes

s

A sequence of data (N byte + acknowledge)

s

A stop condition (P))

ACK = Acknowledge;

S = Start;

P = Stop;

A = Address;

B = Auto Increment

EXAMPLES

No Incremental Bus

The TDA7448 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental

bus), N-data (all these data concern the subaddress selected), a stop condition.

Incremental Bus

The TDA7448 receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus):

now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000"

to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the

subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.

DATA BYTES

Address= 88 (HEX) (10001000): ADDR open; 8A (HEX) (10001010): connect to supply

FUNCTION SELECTION: subaddress

B=1: INCREMENTAL BUS; ACTIVE

B=0: NO INCREMENTAL BUS

X= DON’T CARE

MSB

LSB

SUBADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

B

0

0

0

0

SPEAKER ATTENUATION OUT 1

X

X

X

B

0

0

0

1

SPEAKER ATTENUATION OUT 2

X

X

X

B

0

0

1

0

SPEAKER ATTENUATION OUT 3

X

X

X

B

0

0

1

1

SPEAKER ATTENUATION OUT 4

X

X

X

B

0

1

0

0

SPEAKER ATTENUATION OUT 5

X

X

X

B

0

1

0

1

SPEAKER ATTENUATION OUT 6

X

X

X

B

0

1

1

0

NOT USED”

X

X

X

B

0

1

1

1

NOT USED

S

1

0

0

0

1

0

0

0

ACK

ACK

DATA

ACK

P

MSB

LSB

MSB

LSB

MSB

LSB

CHIP ADDRESS

D96AU420

X

DATA

SUBADDRESS

DATA 1 to DATA n

XXB

S

1

0

0

0

1

0

0

0

ACK

ACK

DATA

ACK

P

MSB

LSB

MSB

LSB

MSB

LSB

CHIP ADDRESS

D96AU421

XD3

SUBADDRESS

DATA

XX

0

D2 D1 D0

S

1

0

0

0

1

0

0

0

ACK

ACK

DATA

ACK

P

MSB

LSB

MSB

LSB

MSB

LSB

CHIP ADDRESS

D96AU422

XD3

SUBADDRESS

DATA 1 to DATA n

XX

1

D2 D1 D0