PSD4235G2 datasheet(12/93 Pages) STMICROELECTRONICS

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Preliminary Information

PSD4000 Series

Pin*

(TQFP

Pin Name Pkg.)

Type

Description

Reset

Active low input. Resets I/O Ports, PLD Micro

⇔Cells, some of

the configuration registers and JTAG registers. Must be active

at power up. Reset also aborts the Flash programming/erase

cycle that is in progress.

PA0-PA7

51-58

I/O

Port A, PA0-7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port

Drain

2. GPLD output.

3. Input to the PLD (can also be PLD input for address A16

and above).

PB0-PB7

61-68

I/O

Port B, PB0-7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. GPLD output.

3. Input to the PLD (can also be PLD input for address A16

and above).

PC0-PC7 41-48

I/O

Port C, PC0-7. This port is pin configurable and has multiple

CMOS

functions:

or Slew

1. MCU I/O — standard output or input port.

Rate

2. External chip select (ECS0-7) output.

3. Input to the PLD (can also be PLD input for address A16

and above).

PD0

I/O

Port D pin PD0 can be configured as:

CMOS

1. ALE or AS input — latches addresses on ADIO0-15 pins

or Open

2. AS input — latches addresses on ADIO0-15 pins on the

Drain

rising edge.

3. Input to the PLD (can also be PLD input for address A16

and above).

PD1

I/O

Port D pin PD1 can be configured as:

CMOS

1. MCU I/O

or Open

2. Input to the PLD (can also be PLD input for address A16

Drain

and above).

3. CLKIN clock input — clock input to the GPLD

Micro

⇔Cells, the APD power down counter and GPLD

AND Array.

PD2

I/O

Port D pin PD2 can be configured as:

CMOS

1. MCU I/O

or Open

2. Input to the PLD (can also be PLD input for address A16

Drain

and above).

3. CSI input — chip select input. When low, the CSI enables

the internal PSD memories and I/O. When high, the

internal memories are disabled to conserve power. CSI

trailing edge can get the part out of power-down mode.

PD3

I/O

Port D pin PD3 can be configured as:

CMOS

1. MCU I/O

or Open

2. Input to the PLD (can also be PLD input for address A16

Drain

and above).

3. WRH — for 16-bit data bus, write to high byte, active low.

PE0

I/O

Port E, PE0. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TMS input for JTAG/ISP interface.

Table 5.

PSD4000

Descriptions

(cont.)

PSD4235G2 Datasheet(PDF) 12 Page - STMicroelectronics

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