TEA7063DP datasheet(8/15 Pages) STMICROELECTRONICS

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3. RECEIVE CHAIN

3.1 A.G.C. In Receive

As described for the transmission chain, also the

receiving gains Gr, from pins 1 and 2 to pin 20,

have a reduction of 6dB when Iline moves from

ILL to ILS (see also paragr. 4).

3.2 Sidetone Compensation

The circuit is provided with a double anti-sidetone

network to optimize both at long and short lines.

In case double antisidetone network is not re-

quested by the application needs, pins 1 and 2

can be connected to each other and 5 external

passive components can be saved (ZALL and

ZRL).

Before entering pins 1 and 2, the received signal

is areduced by the two attenating networks:

- ZALL/ZRL to pin 1 for long lines sidetone com-

pensation,

- ZALS/ZRS to pin 2 for short lines sidetone com-

pensation.

ZRL and ZRS define the total receive gains:

V20

V16

= Gr •

ZRL

+ ZALL

for

long lines

V20

V16

=( Gr − 6dB ) •

ZRS

+ ZALS

for short lines

ZALL and ZALS define the sidetone compensa-

tion of the circuit.

The equivalent balancing impedance is given by

the formula:

ZAL = K

• ZALS + (1 - K) • ZALL

where:

-K = 0 at ILINE = ILL or lower (long line)

-K varies linearly from 0 to 1 with Iline between

ILL and ILS

-K = 1 at ILINE = ILS or higher (short line)..

Calculations to define ZALL and ZALS are:

ZALL = 70

• R5 •

Zline

( long ) ⁄⁄ Zext ⁄⁄ Zint ⁄⁄ Zout

Zout

ZALL = 70

• R5 •

Zline ( short ) ⁄⁄ Zext ⁄⁄ Zint ⁄⁄ Zout

Zout

where:

-Zext = R6//C4//(Zelectret) (at pin 13)

-Zint =10K

Ω//8.5nF (internal impedance)

-Zout = 10.65

• Z4 (at pin 3; see paragr. 2.2)

- Zline (short) and (long) are the impedances of

the line at minimum and naximum line lenght

- R5 = 5.1K

Ω ±1% (typically)

3.3 AC Impedance

The total AC impedance of the circuit to the line

is:

ZAC = Zout//Zint//Zext (ZALS, ZALL >>ZAC)

3.4 Receive Mute (and confidence level)

When the receive channel is muted (Vpin 14 >

2.7V) the receive gain is reduced of 60dB minimum.

Figure 6

TEA7063

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