MC13224VR2 datasheet(21/48 Pages) FREESCALE

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MC13224V Product Preview, Rev. 1.0

Freescale Semiconductor

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Normal mode — The simplest SSI mode transfers data in one time slot per frame

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Network mode — Creates a Time Division Multiplexed (TDM) network, such as a TDM CODEC

network or a network of DSPs

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Gated Clock mode — Connects to SPI-type interfaces on MCUs or external peripheral chips

With its multi-modes, the SSI can be programmed for two very useful functions:

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A second SPI port augmenting the MC13224V SPI module

•I2S interface - the SSI is capable of generating the required clock frequencies and data format to

drive a serial stereo audio DAC

The SSI includes the following features:

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Synchronous transmit and receive sections with shared internal/external clocks and frame syncs,

operating in Master or Slave mode.

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Normal mode operation using frame sync

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Network mode operation allowing multiple devices to share the port with as many as thirty-two

time slots

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Gated Clock mode operation requiring no frame sync

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SSI clock source is Peripheral Clock (typically 24 MHz); maximum SSI transfer rate is 6.0 MHz

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Separate Transmit and Receive FIFOs. Each of which is 8x24 bits

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Programmable data interface modes including I2S, LSB, MSB aligned

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Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)

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Program options for frame sync and clock generation

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Programmable I2S modes (Master, Slave)

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Programmable internal clock divider

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Time Slot Mask Registers for reduced CPU overhead (for Tx and Rx both)

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SSI power-down feature

4.8

Analog-to-Digital Converter (ADC) Module

The MC13224V ADC module provides two 12-bit analog-to-digital converters (ADC_1 and ADC_2) with

eight external channels (ADC7 - ADC0) that can be multiplexed to either ADC. ADC_1 can also sample

a battery reference voltage for monitoring purposes. External pins (ADC2_VREFH, ADC2_VREFL,

ADC1_VREFH, and ADC1_VREFL) are provided for independent ADC reference voltages. The

minimum sample time is 20 µs. Figure 8 shows a block diagram of the ADC module.

Each ADC can be programmed to scan multiple selected channels on a timed basis. The primary clock to

the ADC module is the peripheral reference clock (typically 24 MHz). For the time period between scan

sequences, the primary clock is first divided by an 8-bit prescale (1-255), and the derived clock drives both

the 32-bit delay timer and the ADC sequencer. Each ADC has its own delay timer and sequencer.

Once a scan sequence has been initiated, all selected channels can be sampled. Registers are provided to

define thresholds that can be enabled for the sampled channels. A threshold can be assigned to a specific

channel and can be programmed to be a less-than or greater-than threshold. Multiple thresholds can be

MC13224VR2 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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