AT91SAM7A3 datasheet(13/39 Pages) ATMEL

13 / 39 page

6042DS–ATARM–14-Dec-06

AT91SAM7A3

Processor and Architecture

7.1

ARM7TDMI Processor

• RISC Processor Based on ARMv4T Von Neumann Architecture

– Runs at up to 60 MHz, providing 0.9 MIPS/MHz

• Two instruction sets

– ARM high-performance 32-bit Instruction Set

– Thumb high code density 16-bit Instruction Set

• Three-stage pipeline architecture

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

7.2

Debug and Test Features

• Integrated EmbeddedICE

™ (embedded in-circuit emulator)

– Two watchpoint units

– Test access port accessible through a JTAG protocol

– Debug communication channel

• Debug Unit

–Two-pin UART

– Debug communication channel interrupt handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

7.3

Memory Controller

• Bus Arbiter

– Handles requests from the ARM7TDMI and the Peripheral Data Controller

• Address Decoder Provides Selection Signals for

– Three internal 1Mbyte memory areas

– One 256 Mbyte embedded peripheral area

• Abort Status Registers

– Source, Type and all parameters of the access leading to an abort are saved

– Facilitates debug by detection of bad pointers

• Misalignment Detector

– Alignment checking of all data accesses

– Abort generation in case of misalignment

• Remap Command

– Remaps the Internal SRAM in place of the embedded non-volatile memory

– Allows handling of dynamic exception vectors

• 16-area Memory Protection Unit

– Individually programmable size between 1K Bytes and 1M Bytes

AT91SAM7A3 Datasheet(PDF) 13 Page - ATMEL Corporation

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