CS2300-CP

DS843PP1

13

5.2.2

CLK_IN Skipping Mode

CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses

skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn bit enables

this function.

634 ms) after CLK_IN is removed (see Figure 7). This is true as long as CLK_IN does not glitch or have

an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a

the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock Out-

put” on page 19. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified

time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL

output will resume.

have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 8). Once CLK_IN

is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be

determined by the ClkOutUnl bit during this time.

continues while the PLL re-acquires lock (see Figure 9). When ClkSkipEn is disabled and CLK_IN is re-

moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only

for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks