AT89C5131A-RDTUM datasheet(118/188 Pages) ATMEL

118 / 188 page

118

4337K–USB–04/08

AT89C5130A/31A-M

20.3

Registers

Table 20-10. SSCON Register

SSCON - Synchronous Serial Control Register (93h)

CR2

SSIE

STA

STO

CR1

CR0

Bit Number

Bit

Mnemonic

Description

CR2

Control Rate bit 2

See .

SSIE

Synchronous Serial Interface Enable bit

Clear to disable SSLC.

Set to enable SSLC.

STA

Start flag

Set to send a START condition on the bus.

ST0

Stop flag

Set to send a STOP condition on the bus.

Synchronous Serial Interrupt flag

Set by hardware when a serial interrupt is requested.

Must be cleared by software to acknowledge interrupt.

Assert Acknowledge flag

Clear in master and slave receiver modes, to force a not acknowledge (high level on

SDA).

Clear to disable SLA or GCA recognition.

Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter

modes.

Set in master and slave receiver modes, to force an acknowledge (low level on SDA).

This bit has no effect when in master transmitter mode.

CR1

Control Rate bit 1

See Table 20-4

CR0

Control Rate bit 0

See Table 20-4

Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write)

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Bit Number

Bit

Mnemonic

Description

SD7

Address bit 7 or Data bit 7.

SD6

Address bit 6 or Data bit 6.

SD5

Address bit 5 or Data bit 5.

SD4

Address bit 4 or Data bit 4.

SD3

Address bit 3 or Data bit 3.

SD2

Address bit 2 or Data bit 2.

AT89C5131A-RDTUM Datasheet(PDF) 118 Page - ATMEL Corporation

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