ARRIAGX datasheet(21/296 Pages) ALTERA

21 / 296 page

Altera Corporation

2–13

May 2008

Arria GX Device Handbook, Volume 1

Arria GX Architecture

PCI Express (PIPE) Receiver Detect

The Arria GX transmitter buffer has a built-in receiver detection circuit

for use in PCI Express (PIPE) mode. This circuit provides the ability to

detect if there is a receiver downstream by sending out a pulse on the

channel and monitoring the reflection. This mode requires a tri-stated

transmitter buffer (in electrical idle mode).

PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)

The Arria GX transmitter buffer supports PCI Express (PIPE) electrical

idles. This feature is only active in PCI Express (PIPE) mode. The

tx_forceelecidle

port puts the transmitter buffer in electrical idle

mode. This port is available in all PCI Express (PIPE) power-down modes

and has specific usage in each mode.

Receiver Path

This section describes the data path through the Arria GX receiver. The

sub-blocks are described in order from the receiver buffer to the

PLD-receiver parallel interface.

Receiver Buffer

The Arria GX receiver input buffer supports the 1.2 V and 1.5 V PCML

I/O standard at rates up to 3.125 Gbps. The common mode voltage of the

receiver input buffer is programmable between 0.85 V and 1.2 V. You

must select the 0.85 V common mode voltage for AC- and DC-coupled

PCML links and 1.2 V common mode voltage for DC-coupled LVDS links.

The receiver has on-chip 100

Ω differential termination for different

protocols, as shown in Figure 2–11. The receiver’s internal termination

can be disabled if external terminations and biasing are provided. The

receiver and transmitter differential termination method can be set

independently of each other.

Figure 2–11. Receiver Input Buffer

100

Termination

Input

Pins

Differential

Input

Buffer

Programmable

Equalizer

ARRIAGX Datasheet(PDF) 21 Page - Altera Corporation

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