AT91SAM9261 datasheet(21/43 Pages) ATMEL

21 / 43 page

6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them

to the new clock

Switch the main clock to the new value.

8.1.3

ETM

™ Memories

The eight ETM9 Medium+ memory map decoder inputs are connected to custom address

decoders and the resulting memory mapping is summarized in Table 8-6.

8.2

External Memories

The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3).

Refer to the memory map in Figure 8-1 on page 16.

Table 8-6.

ETM9 Memory Mapping

Product Resource

Area

Access Type

Start Address

End Address

SRAM

Internal

Data

0x0000 0000

0x002F FFFF

SRAM

Internal

Fetch

0x0000 0000

0x002F FFFF

ROM

Internal

Data

0x0040 0000

0x004F FFFF

ROM

Internal

Fetch

0x0040 0000

0x004F FFFF

External Bus Interface

External

Data

0x1000 0000

0x8FFF FFFF

External Bus Interface

External

Fetch

0x1000 0000

0x8FFF FFFF

User Peripherals

Internal

Data

0xF000 0000

0xFFFF BFFF

System Peripherals

Internal

Data

0xFFFF C000

0xFFFF FFFF

AT91SAM9261 Datasheet(PDF) 21 Page - ATMEL Corporation

AT91SAM9261 Datasheet(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL