Data Sheet #: TM052

Page 13 of 36

Rev: 03

Date: 11/07/08

Register Descriptions and Operation continued

Op_Mode, 0x05 (R/W)

Bit 7 ~ Bit 5

Bit 4

Bit 3 ~ Bit 0

Reserved

Master or Slave Mode

Free Run, Locked, or Hold Over:

1: Master

0000: Free Run mode

0: Slave

0001: Locked on Ref1

(Read Only)

0010: Locked on Ref2

0011: Locked on Ref3

0100: Locked on Ref4

0101 - 1000: Not Used

1001 - 1111: Hold Over

Max_Pullin_Range, 0x06 (R/W)

Bit 7 ~ Bit 0

Maximum pull-in range in 0.1 ppm unit

This register should be set according to the values specified by the standards (GR-1244) appropriate for the particular stratum of

operation. The power-up default value is 10 ppm. (= 4.6ppm aging + 4.6 ppm pullin + margin).

M/S_Activity, 0x07 (R)

Bit 7 ~ Bit 4

Bit 3 ~ Bit 0

Reserved

Cross reference activity

0000: No signal

0001: 8kHz

0010:1.544 MHz

0011:2.048MHz

0100: 12.96MHz

0101: 19.44MHz

0110: 25.92MHz

0111: 38.88MHz

1000: 51.84MHz

1001: 77.76MHz

1010-1111: Reserved

Indicates signal presence and auto-detected frequency for the M/S REF input.

Ref_Activity, 0x08 (R)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ref4 activity

ref3 activity

ref2 activity

ref1 activity

0: off

0: off

0: off

0: off

1: on

1: on

1: on

1: on

0: off

0: off

0: off

0: off

Each bit indicates the presence of a signal for that reference.

When the device is in slave mode, it will lock to the M/S REF, independent of the values written to BITS 3 - 0 of the Op_mode

register. The operational mode and reference selection written to Bits 3 - 0 while in slave mode will, however, take effect when the

device is made the master.

When bit 1 of the Ctl_Mode register is reset (automatic reference and mode selection) and the device is in master mode, BITS 3 -

0 of the Op_Mode register become read-only.