STC3500 datasheet(39/48 Pages) CONNOR-WINFIELD

39 / 48 page

Preliminary Data Sheet: TM060

Page 39 of 48

Rev: P06

Date: 11/22/04

Application Notes continued

Control Modes

The STC3500 device may be controlled and interfaced in a pure hardware mode with pin signals, or via SPI or parallel

bus/register access. With register access, the device can in turn be operated in a manual control mode, or automatic

control and reference selection mode. Hardware mode is most suitable for simple environments where minimal external

intelligence is desired. Register access provides more detailed visibility and control for references and general

synchronization operation. These three main operating environments are detailed as follows:

Hardware Control Interfaces

Figure 12

HM_Ref

M/S

Sel1

Sel2

Sel3

LOS

LOL

Hold_Avail

Reset

STC3500

Outputs

Inputs

Master/Slave

Reference/

Operational

Mode Select

Reset

Sel0

Vdd3.3

BITS_Sel

BITS output

frequency select

Hardware Control – The device interfaces for hardware control are shown in Figure 12.

Reset may be pulled low for a minimum of 100nS during chip start-up (or any other desired time) to initialize the full

device state. However, power-up will also perform a reset, so in a minimal configuration, Reset may be tied input high.

The BITS clock output frequency is selected by the BITS_Sel pin. When BITS_Sel = 1, the BITS frequency is 1.544

MHz, and when BITS_Sel = 0, the BITS frequency is 2.048 MHz.

M/S - Determines the master or slave mode. Set to “1” for a master, and “0” for a slave. Master/slave switches should

be performed with minimal delay between switching the states of each of the two devices. This can be easily

accomplished, for example, by controlling the master/slave state with a single signal, coupled to one of the devices

through an inverter.

For simplex operation, the device should be in Master mode - set M/S to “1”.

HM_Ref - Set to “1” for hardware control of reference selection and operational mode.

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