LT3682 datasheet(21/24 Pages) LINER

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LT3682

3682f

APPLICATIONS INFORMATION

PCB Layout

For proper operation and minimum EMI, care must be taken

during printed circuit board layout. Figure 10 shows the

recommended component placement with trace, ground

plane and via locations. Note that large, switched currents

ﬂow in the LT3682’s VIN, SW and PGND pins, the catch

diode and the input capacitor (CIN). The loop formed by

these components should be as small as possible. These

components, along with the inductor and output capacitor

(COUT), should be placed on the same side of the circuit

board, and their connections should be made on that layer.

All connections to GND should be made at a common

star ground point or directly to a local, unbroken ground

plane below these components. The SW and BOOST nodes

should be laid out carefully to avoid interference. If the

part is synchronized externally using the SYNC pin, care

must be taken laying out this signal to avoid interference

with sensitive nodes, especially VC, FB, and RT. Finally,

keep the FB, RT, and VC nodes small so that the ground

traces will shield them from the SW and BOOST nodes.

The exposed pad Pin 13 on the bottom of the package

acts as a heat sink and must be soldered to the ground

node. To keep thermal resistance low, extend the ground

plane as much as possible and add thermal vias under and

near the LT3682 to any additional ground planes within

the circuit board and on the bottom side. Keep in mind

that the thermal design must keep the junctions of the

IC below the speciﬁed absolute maximum temperature

of 125°C.

High Temperature Considerations

The PCB must provide heat sinking to keep the LT3682

cool. The exposed pad on the bottom of the package must

be soldered to a copper area, which in turn should be

tied to large copper layers below with thermal vias; these

layers will spread the heat dissipated by the LT3682. Place

additional vias to reduce thermal resistance further. With

these steps, the thermal resistance from die (or junction)

to ambient can be reduced to

θJA = 35°C/W or less. With

100 LFPM airﬂow, this resistance can fall by another 25%.

Further increases in airﬂow will lead to lower thermal

resistance. Because of the large output current capability of

Figure 10. A Good PCB Layout Ensures Proper, Low EMI Operation

the LT3682, it is possible to dissipate enough heat to raise

the junction temperature beyond the absolute maximum of

125°C. When operating at high ambient temperatures, the

maximum load current should be derated as the ambient

temperature approaches these maximums. If the junction

temperature reaches the thermal shutdown threshold, the

part will stop switching to prevent internal damage due

to overheating.

Power dissipation within the LT3682 can be estimated

by calculating the total power loss from an efﬁciency

measurement. The die temperature is calculated by

multiplying the LT3682 power dissipation by the thermal

resistance from junction to ambient.

Other Linear Technology Publications

Application Notes 19, 35 and 44 contain more detailed

descriptions and design information for buck regulators

and other switching regulators. The LT1376 data sheet

has a more extensive discussion of output ripple, loop

compensation and stability testing. Design Note 318

shows how to generate a bipolar output supply using a

buck regulator.

3682 F10

VIN

GND

VOUT

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