Family

Device

Utilization

Performance

COMB

SEQ

Total

SX-A

SX32A-3

760 (42%)

510 (48%)

1270 (44%)

77 MHz

APA150-STD

n/a

n/a

2212 (36%)

42 MHz

Axcelerator

AX500-3

695 (13%)

507 (19%)

1202 (15%)

79 MHz

Verification and Compliance

Complete functional and timing simulation has been performed on the G704-E1 Framer using ModelSim 5.5d. This core has also been used successfully in customer

designs.

Signal Descriptions

The following signal descriptions define the IO signals.

Signal

Direction

Description

ClkSys

Input

System clock: This is the only clock source for the whole G704-E1 core

resn

Input

Asynchronous System Reset: active low

CfgFSync.SyncMode[1:0]

Input

Configuration of Frame Synchronizer:

“00”: transparent (no FSync generated)

“01”: free run (generate dummy FSync)

“10”: use external FSync

“11”: fully automatic sync (G.706)

CfgFSync.ForceResync

Input

User controlled resync: When toggled form ‘0’ to ‘1’, a resync is initialized

CfgFSync.AutoResync

Input

Automatic resync after loss of sync: ‘1’: Automatic resync ON ( ‘0’: OFF )

CfgFSync.FAImprove_411

Input

‘0’: Improved BasicFrame alignment disabled ‘1’: Use improved BasicFrame

alignment procedure as in $4.1.1 of G.704/Note 1 (check FA bit 2 of nFAS

frames)

CfgFSync.MF_Mode

‘0’: MultiFrame alignment search disabled (only Basic-Frame search)

‘1’: MultiFrame alignment search enabled

CfgFSync.MF_SyncMode

Input

‘0’: use parallel BFA search (G.706)

‘1’: reuse primary BFA search (PTT simplified search path)

CfgFSync.MFA_Check

Input

‘0’: MultiFrame alignment loss checking process disabled

‘1’: MultiFrame alignment checking process enabled (if 3 consecutive MFA not

found while MFSyncState = InSync, then MFSyncState <= Hunt)

CfgFSync.CRC4_Mode

Input

‘0’: CRC4 Error limit of <= 915 disabled

‘1’: CRC4 Error limit checking enabled

CfgFan.CRC_CountEbl

Input

‘0’: CRC4 Error counter enabled

‘1’: CRC4 Error counter disabled

CfgFan.FAS_Count_Ebl

Input

‘0’: FAS Error counter enabled

‘1’: FAS Error counter disabled

CfgFan.E_Count_Ebl

Input

‘0’: E-Bit counter enabled

‘1’: E-Bit counter disabled

CfgOverhead.Si_E1

Input

E1 / Si of FAS frame

CfgOverhead.Si_E2

Input

E2 / Si of non FAS frame

CfgOverhead.A-Bit

Input

A-Bit

CfgOverhead.InsertEbl[4:0]

Input

Insert enable pattern related to Sa bits

CfgOverhead.saBitsMF[1:8][4:0]

Input

Sa4...Sa8 bits

Note: When FrameRef.MF.MFSyncState NOT = InSync, then only SaBitsMF(1)

will be inserted.

CfgFBuild.CRC4_MFMode

Input

‘0’: CRC4 MultiFrame Mode disabled

‘1’: CRC4 MultiFrame Mode enabled

CfgFBuild.BuildMode[1:0]

“0x”: transparent, “10”: synchronize BFA phase, “11”: generate BFA phase

(Note: when NOT transparent, a new MultiFrame is generated)

IntSrc_FSync.BFA.Sync

Output

Pulse @ ‘1’ when entering state InSync

IntSrc_FSync.BFA.SyncLoss

Output

Pulse @ ‘1’ when leaving state InSync

IntSrc_FSync.MFA.SyncEntry

Output

Pulse @ ‘1’ when entering state InSync

IntSrc_FSync.MFA.MFSync

Output

Pulse @ ‘1’ at begin of each MultiFrame