RTSX-S datasheet(21/84 Pages) ACTEL

21 / 84 page

RTSX-S RadTolerant FPGAs

v2.2

2-7

I/O Specifications

Pin Descriptions

Supply Pins

GND

Ground

Low supply voltage.

VCCI

Supply Voltage

Supply voltage for I/Os. See Table 2-1 on page 2-1.

VCCA

Supply Voltage

Supply voltage for Array. See Table 2-1 on page 2-1.

Global Pins

CLKA/B

Routed Clock A and B

These pins are clock inputs for clock distribution

networks. Input levels are compatible with standard TTL,

LVTTL, 3.3V PCI, or 5V PCI specifications. The clock input

is buffered prior to clocking the R-cells. When not used,

this pin must be set Low or High on the board. When

used, this pin should be held Low or High during power-

up to avoid unwanted static power.

For RT54SX72S, these pins can be configured as user I/Os.

When used, this pin offers a built-in programmable pull-

up or pull-down resistor active during power-up only.

QCLKA/B/C/D

Quadrant Clock A, B, C, and D / I/O

These four pins are the quadrant clock inputs and are

only found on the RT54SX72S. They are clock inputs for

clock distribution networks. Input levels are compatible

with

standard

TTL,

LVTTL,

3.3V

PCI

specifications. Each of these clock inputs can drive up to

a quarter of the chip, or they can be grouped together to

drive multiple quadrants. The clock input is buffered

prior to clocking the core cells.

These pins can be configured as user I/Os. When not

used, these pins must not be left floating. They must be

set Low or High on the board. When used, this pin offers

a built-in programmable pull-up or pull-down resistor,

active during power-up only.

HCLK

Dedicated (Hardwired) Array Clock

This pin is the clock input for sequential modules. Input

levels are compatible with standard TTL, LVTTL, 3.3V PCI or

5V PCI specifications. This input is buffered prior to

clocking the R-cells. It offers clock speeds independent of

the number of R-cells being driven. When not used, this

pin must not be left floating. It must be set to Low or High

on the board. When used, this pin should be held Low or

High during power-up to avoid unwanted static power.

JTAG/Probe Pins

PRA/PRB1 I/O,

Probe A/B

The probe pin is used to output data from any user-

defined design node within the device. This independent

diagnostic pin can be used in conjunction with the other

probe pin to allow real-time diagnostic output of any

signal path within the device. The probe pin can be used

as a user-defined I/O when verification has been

completed.

The

pin’s

probe

capabilities

can

permanently disabled to protect programmed design

confidentiality.

TCK1, I/O

Test Clock

Test clock input for diagnostic probe and device

programming. In flexible mode, TCK becomes active

when the TMS pin is set Low (Table 2-32 on page 2-35).

This pin functions as an I/O when the boundary scan

state machine reaches the “logic reset” state.

TDI1, I/O

Test Data Input

Serial input for boundary scan testing and diagnostic

probe. In flexible mode, TDI is active when the TMS pin is

set Low (Table 2-32 on page 2-35). This pin functions as

an I/O when the boundary scan state machine reaches

the “logic reset” state.

TDO1, I/O

Test Data Output

Serial output for boundary scan testing. In flexible mode,

TDO is active when the TMS pin is set Low (Table 2-32 on

page 2-35). This pin functions as an I/O when the

boundary scan state machine reaches the "logic reset"

state. When Silicon Explorer II is being used, TDO will act

as an output when the "checksum" command is run. It

will return to user I/O when "checksum" is complete.

TMS1

Test Mode Select

The TMS pin controls the use of the IEEE 1149.1

boundary scan pins (TCK, TDI, TDO, TRST). In flexible

mode when the TMS pin is set Low, the TCK, TDI, and

TDO pins are boundary scan pins (Table 2-32 on page 2-

35). Once the boundary scan pins are in test mode, they

will remain in that mode until the internal boundary

scan state machine reaches the “logic reset” state. At this

point, the boundary scan pins will be released and will

function as regular I/O pins. The “logic reset” state is

reached five TCK cycles after the TMS pin is set High. In

dedicated test mode, TMS functions as specified in the

IEEE 1149.1 specifications.

1. These pins should be terminated with a 70

Ω resistor to preserve probing capabilities.

RTSX-S Datasheet(PDF) 21 Page - Actel Corporation

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