Functional Description

This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. There-

fore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface. Please

consult the appropriate standards document for all external signaling.

TX MASTER

The TX master is responsible for polling the phys and internal queues in order to send cells to the slave device.

Signal

Width

Direction

Description

EGR_CLK

1

Input

25/50 MHz Utopia Clock for all registers in this block

EGR_DATA

8/16

Output

Utopia Data Bus. 8 or 16 bits selectable

EGR_ADDR

5

Output

Utopia Address Bus used for polling

EGR_SOC

1

Output

Utopia Start of Cell signal used to flag the first byte/word in the cell

EGR_ENB_N

1

Output

Utopia Enable signal used for selection

EGR_CLAV

1

Input

Utopia Cell Available signal used to indicate that the phy has room for a cell

EGR_PRTY

1

Output

Utopia Parity used for odd parity on EGR_DATA

RD_DATA

N*8/16

Input

Internal FIFO Bus

RD_ENB

N

Output

Internal FIFO Read Enable Signal

DECREMENT

N

Output

Internal signal used to decrement cell available counter

EMPTY

N

Input

Internal FIFO Empty flag

FLAG

N

Input

Internal signal used to indicate that there is a cell waiting to be sent for this queue

Table 1: TX Master Signal List

TX FIFO

The TX FIFO contains the RAM FIFO and the packet counter block. The packet counter is responsible for generating the cell available flags for the rest of the design.

Every time a cell is written into the FIFO increment gets set and the cell count goes up, and when a cell is read decrement is set and the cell count goes down. The

cell available “flag” is set when there is at least one cell in the FIFO that needs to be read. The FIFO operates in synchronous and asynchronous systems and can

hold 9 cells. There is one FIFO per PHY polled.

Signal

Width

Direction

Description

WR_CLK

1

Input

System Clock for all registers in this block

WR_DATA

N*8/16

Input

Write data bus for FIFO

WR_ENB

N

Input

Write enable signal for FIFO

INCREMENT

N

Input

Increment signal for packet counter block

A_FULL

N

Output

Almost full for FIFO indicates that the FIFO does not have enough room for an

additional cell.

RD_CLK

1

Input

Read clock for the FIFO = EGR_CLK for all read registers in this block

RD_DATA

N*8/16

Output

Read data bus for the FIFO

RD_ENB

N

Input

Read enable signal for the FIFO

DECREMENT

N

Input

Decrement signal for packet counter block

EMPTY

N

Output

Indicates when FIFO is empty

Table 2: TX FIFO Signal List