APA600-FGGES datasheet(33/174 Pages) ACTEL

33 / 174 page

ProASICPLUS Flash Family FPGAs

v5.7

1-27

Design Environment

The ProASICPLUS family of FPGAs is fully supported by

both Actel's Libero® Integrated Design Environment

(IDE) and Designer FPGA Development software. Actel

Libero IDE is an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log

files, and passing necessary design data among tools.

Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment (see Actel’s

website for more information about Libero IDE). Libero

IDE includes Synplify® AE from Synplicity®, ViewDraw®

AE from Mentor Graphics®, ModelSim® HDL Simulator

from Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD®, PALACE™ AE Physical Synthesis from

Magma, and Designer software from Actel.

PALACE is an effective tool when designing with

ProASICPLUS. PALACE AE Physical Synthesis from Magma

takes an EDIF netlist and optimizes the performance of

ProASICPLUS devices through a physical placement-driven

process, ensuring that timing closure is easily achieved.

Actel's Designer software is a place-and-route tool that

provides a comprehensive suite of back-end support

tools for FPGA development. The Designer software

includes the following:

•

Timer – a world-class integrated static timing

analyzer and constraints editor that support

timing-driven place-and-route

•

NetlistViewer – a design netlist schematic viewer

•

ChipPlanner – a graphical floorplanner viewer and

editor

•

SmartPower – allows the designer to quickly

estimate the power consumption of a design

•

PinEditor – a graphical application for editing pin

assignments and I/O attributes

•

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in a

spreadsheet format

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel’s back-annotation

flow is compatible with all the major simulators. Another

tool included in the Designer software is the SmartGen

macro

builder,

which

easily

creates

popular

and

commonly used logic functions for implementation into

your schematic or HDL design.

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

ISP

The user can generate *.bit or *.stp programming files

from the Designer software and can use these files to

program a device.

ProASICPLUS devices can be programmed in-system. For

more information on ISP of ProASICPLUS devices, refer to

the In-System Programming ProASICPLUS Devices and

Performing Internal In-System Programming Using Actel’s

ProASICPLUS Devices application notes. Prior to being

programmed for the first time, the ProASICPLUS device I/Os

are in a tristate condition with the pull-up resistor option

enabled.

APA600-FGGES Datasheet(PDF) 33 Page - Actel Corporation

APA600-FGGES Datasheet(HTML) 33 Page - Actel Corporation

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